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Esnek Ardışık-Çıkarımlı Kutupsal Kod Çözücünün FPGA Gerçeklemesi

Year 2023, Volume: 10 Issue: 1, 76 - 81, 31.05.2023
https://doi.org/10.35193/bseufbd.1140235

Abstract

Kanal kapasitesi, bir kanalın iletilebileceği maksimum bit hızını ifade eder. Kutupsal kodlar, simetrik ikili girişli, hafızasız kanallar için sonsuz blok uzunluğunda kanal kapasitesine erişebilen ilk hata düzeltme kodlarıdır. Kutupsal kodların bu başarımı ile 5. Nesil Yeni Radyo Haberleşme standardında kullanımına karar verilmiştir. Bu çalışmada, farklı blok uzunluklarında ve farklı kod oranlarında kutupsal kodların, ardışık-çıkarım (successive-cancellation) kod çözücü algoritması alanında programlanabilir kapı dizileri (Field-programmable gate array, FPGA) ile gerçeklemesi anlatılmıştır.

Thanks

Bu çalışma TÜBİTAK 122E236 numaralı projesi kapsamında desteklenmiştir.

References

  • Arıkan, E. (2009). Channel Polarization: A Method for Constructing Capacity-Achieving Codes for Symmetric Binary-Input Memoryless Channels. IEEE Transactions on Information Theory, 55 (7), 996–1009.
  • 3GPP TSG RAN WG1 Meeting #87. (2016). On the hardware implementation of channel decoders for short block lengths. Reno, Nevada, USA.
  • Tal, I., & Vardy, A. (2015). List Decoding of Polar Codes, IEEE Transactions on Information Theory, 61 (5), 2213-2226.
  • Tal, I., & Vardy, A. (2011). List Decoding of Polar Codes. International Symposium on Information Theory Proceedings, 31 July - 05 August, St. Petersburg, Russia, 1-5.
  • Leroux, C., Tal, I., Vardy, A., & Gross, W., J. (2011). Hardware architectures for successive cancellation decoding of polar codes. IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP), 22-27 May, Prague, Czech Republic, 1665-1668.
  • Pamuk, A. (2011). An FPGA implementation architecture for decoding of polar codes. 8th International Symposium on Wireless Communication Systems, 06-09 November, Aachen, Germany, 1665-1668.
  • Sarkis, G., Giard, P., Vardy, A., Thibeault, C., & Gross, W., J. (2016). Fast List Decoders for Polar Codes. IEEE Journal on Selected Areas in Communications, 34 (2), 318-328.
  • Dizdar, O., & Arıkan, E. (2016). A High-Throughput Energy-Efficient Implementation of Successive Cancellation Decoder for Polar Codes Using Combinational Logic. IEEE Transactions on Circuits and Systems I: Regular Papers, 63 (3), 436-447.
  • Le Gal, B., Leroux C., & Jego C. (2017). Successive Cancellation Decoder for Very Long Polar Codes. IEEE International Workshop on Signal Processing Systems, 03-05 October, Lorient, France, 1-6.
  • Arlı, A. Ç., Çolak, A., & Gazi O. (2017). The implementation of a successive cancellation polar decoder on Xilinx System Generator. 24th IEEE International Conference on Electronics, Circuits and Systems, 05-08 December, Batumi, Georgia, 372-376.
  • Mazo,J. E. (1975). Faster-than-Nyquist signaling. The Bell System Technical Journal, 54 (8), 1451– 1462.
  • A. Balatsoukas-Stimming & M. B. Parizi & A. Burg (2015). LLR-Based Successive Cancellation List Decoding of Polar Codes. IEEE Transactions on Signal Processing, 63(19), 5165-5179.

FPGA Implementation of Flexible Successive-Cancellation Polar Decoder

Year 2023, Volume: 10 Issue: 1, 76 - 81, 31.05.2023
https://doi.org/10.35193/bseufbd.1140235

Abstract

Channel capacity refers to the maximum bit rate at which a channel can be transmitted. Polar codes were the first error correcting codes to achieve infinite block length channel capacity for symmetric binary input, memoryless channels. This achievement of polar codes has been decided to be used in the 5th Generation New Radio Communication standard. In this study, the implementation of the successive-cancellation decoder algorithm of polar codes at different block lengths and different code rates with field programmable gate arrays (FPGA) is explained.

References

  • Arıkan, E. (2009). Channel Polarization: A Method for Constructing Capacity-Achieving Codes for Symmetric Binary-Input Memoryless Channels. IEEE Transactions on Information Theory, 55 (7), 996–1009.
  • 3GPP TSG RAN WG1 Meeting #87. (2016). On the hardware implementation of channel decoders for short block lengths. Reno, Nevada, USA.
  • Tal, I., & Vardy, A. (2015). List Decoding of Polar Codes, IEEE Transactions on Information Theory, 61 (5), 2213-2226.
  • Tal, I., & Vardy, A. (2011). List Decoding of Polar Codes. International Symposium on Information Theory Proceedings, 31 July - 05 August, St. Petersburg, Russia, 1-5.
  • Leroux, C., Tal, I., Vardy, A., & Gross, W., J. (2011). Hardware architectures for successive cancellation decoding of polar codes. IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP), 22-27 May, Prague, Czech Republic, 1665-1668.
  • Pamuk, A. (2011). An FPGA implementation architecture for decoding of polar codes. 8th International Symposium on Wireless Communication Systems, 06-09 November, Aachen, Germany, 1665-1668.
  • Sarkis, G., Giard, P., Vardy, A., Thibeault, C., & Gross, W., J. (2016). Fast List Decoders for Polar Codes. IEEE Journal on Selected Areas in Communications, 34 (2), 318-328.
  • Dizdar, O., & Arıkan, E. (2016). A High-Throughput Energy-Efficient Implementation of Successive Cancellation Decoder for Polar Codes Using Combinational Logic. IEEE Transactions on Circuits and Systems I: Regular Papers, 63 (3), 436-447.
  • Le Gal, B., Leroux C., & Jego C. (2017). Successive Cancellation Decoder for Very Long Polar Codes. IEEE International Workshop on Signal Processing Systems, 03-05 October, Lorient, France, 1-6.
  • Arlı, A. Ç., Çolak, A., & Gazi O. (2017). The implementation of a successive cancellation polar decoder on Xilinx System Generator. 24th IEEE International Conference on Electronics, Circuits and Systems, 05-08 December, Batumi, Georgia, 372-376.
  • Mazo,J. E. (1975). Faster-than-Nyquist signaling. The Bell System Technical Journal, 54 (8), 1451– 1462.
  • A. Balatsoukas-Stimming & M. B. Parizi & A. Burg (2015). LLR-Based Successive Cancellation List Decoding of Polar Codes. IEEE Transactions on Signal Processing, 63(19), 5165-5179.
There are 12 citations in total.

Details

Primary Language Turkish
Subjects Engineering
Journal Section Articles
Authors

Muhammet Fatih Sertkaya 0000-0001-5985-2724

Enver Çavuş 0000-0002-7203-9700

Publication Date May 31, 2023
Submission Date July 8, 2022
Acceptance Date February 19, 2023
Published in Issue Year 2023 Volume: 10 Issue: 1

Cite

APA Sertkaya, M. F., & Çavuş, E. (2023). Esnek Ardışık-Çıkarımlı Kutupsal Kod Çözücünün FPGA Gerçeklemesi. Bilecik Şeyh Edebali Üniversitesi Fen Bilimleri Dergisi, 10(1), 76-81. https://doi.org/10.35193/bseufbd.1140235