Design of Power and Area Efficient Carry Skip Adder and FIR filter Implementation

Year 2023, Volume: 10 Issue: 1, 81 - 89, 31.01.2023

Govındaraj V , Ezhılazhagan Chenguttuvan , Dhanasekar Subramanıyam

https://doi.org/10.31202/ecjse.1162711

Abstract

Adders are used in arithmetic and logic units (ALUs) as a key building block and many blocks of microprocessor chips critical path adders occupy an important place. Hence reducing power, area and increasing the speed of adders is significantly important. This paper proposes a modified structure of Carry Skip Adder (CSKA) with reduction in consumption of power and area without affecting the speed when compared with the conventional adder strctures. In order to get better effectiveness of the modified CSKA by including concatenation, incrementation schemes and variable latency for the proposed hybrid structure, which reduces the power utilized without affecting the operating speed of the adder. The modified structure in CSKA helps in improving the slack time which further reduces the voltage with the parallel structure. Experimental results show that the 32 bit implementation of proposed adder has a significant power reduction of 42.% and 38.3%, area reduction of 27% and 18.3% with respect to Conventional CSKA and CI CSKA adder with a little over ahead in delay. The proposed adder is used to implement a 5 tap FIR filter which shows a significant reduction in power consumption and area.

Keywords

Carry Skip Adder, Power Consumption, FIR, BEC

Design of Power and Area Efficient Carry Skip Adder and FIR filter Implementation

Abstract

Adders are used in processing units such as Arithmetic and Logic Units (ALUs) as an essential building block, and in many blocks of microprocessor chips critical path, adders occupy an important place. Hence reducing power, area and increasing the speed of adders are significantly important. This paper proposes a modified structure of Carry Skip Adder (CSKA) with a reduction in consumption of power and area without affecting the speed when compared with the conventional adder structures. In order to get better effectiveness of the modified CSKA by including concatenation, incrementation schemes, and variable latency for the proposed hybrid structure, which reduces the power utilized without affecting the operating speed of the adder. The modified structure in CSKA helps in improving the slack time, which further reduces the voltage with the parallel structure. Experimental results show that the 32-bit implementation of the proposed adder has a significant power reduction of 42% and 38.3%, area reduction of 27%, and 18.3% with respect to Conventional CSKA and CI CSKA adder with a little over ahead in delay. The proposed adder is used to implement a 5-tap FIR filter which shows a significant reduction in power consumption and area.

Keywords

Carry Skip Adder, Power Consumption, FIR, Binary to Excess Code convertor.

References

• Alioto M. and Palumbo G 2003, “A simple strategy for optimized design of one-level carry-skip adders‟, IEEE Trans. Circuits Syst. I, Fundam. Theory Appl., vol. 50, no. 1, 141–148.
• Chen et al. Y 2010, “Variable-latency adder (VL-adder) designs for low power and NBTI tolerance”, IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 18, no. 11, 1621–1624.
• Chen Y., Li H., Li J., and Koh C.K 2007, “Variable-latency adder (VL-adder): New arithmetic circuit design practice to overcome NBTI”, ACM/IEEE Int. Symp. Low Power Electron. Design (ISLPED), 195–200.
• Chirca et al K 2004, “A static low-power, high-performance 32-bit carry skip adder”, in Proc. Euromicro Symp. Digit. Syst. Design (DSD),615–619.
• Gayles E., Owens R. M., and Irwin M. J 1996, “Low power circuit techniques for fast carry-skip adders”, Proc. 1996 Midwest Symp. Circuits and Systems,87-90.
• Ghosh S. and Roy K. 2008, “Exploring high-speed low-power hybrid arithmetic units at scaled supply and adaptive clock-stretching”, in Proc. Asia South Pacific Design Autom. Conf. (ASPDAC),635–640.
• Guyot A., Hochet B., and Muller J.M 1987, “A way to build efficient carry skip adders”, IEEE Trans. Comput., vol. C-36, no. 10, 1144–1152.
• Harris D 2003, “A taxonomy of parallel prefix networks”, in Proc. IEEE Conf.Rec. 37th Asilomar Conf. Signals, Syst., Comput., vol. 2. , 2213- 2217.
• Jia et al S 2003, “Static CMOS implementation of logarithmic skip adder”, in Proc. IEEE Conf. Electron Devices Solid-State Circuits,509–512.
• Kim Y. and Kim L.-S, 2001, “64-bit carry-select adder with reduced area”, Electron. Lett., vol. 37, no. 10,614– 615.
• Kogge P. M. and Stone H. S. 1973, “A parallel algorithm for the efficient solution of a general class of recurrence equations”, IEEE Trans. Comput., vol. C- 22, no. 8,786–793.
• Lehman M. and Burla N. 1961, “Skip techniques for high-speed carry propagation in binary arithmetic units”, IRE Trans. Electron. Comput. vol. EC-10, no. 4, 691–698.
• Majerski S. 1967, “On determination of optimal distributions of carry skips in adders”, IEEE Trans. Electron. Comput., vol. EC-16, no. 1, 45–58.
• Milad Bahadori, Mehdi Kamal, Ali Afzali-Kusha and Massoud Pedram 2015, “High-Speed and Energy-Efficient Carry Skip Adder Operating Under a Wide Range of Supply Voltage Levels”, IEEE transsactions on Very Large Scale Integration (VLSI) systems, vol. 24, no. 2, 421-433.
• Nagendra C., Irwin M. J. and Owens R. M. 1996, “Area-time-power tradeoffs in parallel adders”, IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 43, no. 10, 689–702.
• Oklobdzija V.G., Zeydel B.R.., Dao H.Q., Mathew S., and Krishnamurthy R 2005, “Comparison of high-performance VLSI adders in the energy-delay space”, IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 13, no. 6, 754–758.
• Parhami B. 2000, “Computer Arithmetic Algorithms and Hardware Designs”, Oxford Univ. Press.
• Ramkumar B. and Harish M Kittur 2012, “Low-Power and Area-Efficient Carry Select Adder”, IEEE Transactions On Very Large Scale Integration (VLSI) Systems, vol. 20, no. 2.
• Ramkumar B., Kittur H.M., and Kannan P. M. 2010, “ASIC implementation of modified faster carry save adder”, Eur. J. Sci. Res., vol. 42, no. 1, 53–58.
• Sakshi Rajput, Gitanjali, Priya Sharma and Garima 2013, “Design of low power and high speed BEC 2248 efficient novel carry select adder”, International Journal of Advances in Engineering & Technology, Vol. 6, no. 1,172-178.
• Turrini S. 1989, “Optimal group distribution in carry-skip adders”, in Proc.9th IEEE Symp. Comput. Arithmetic, 96–103.
• Y. S. Lin and D. Radhakrishnan, "Delay Efficient 32-bit Carry-Skip Adder," 2006 13th IEEE International Conference on Electronics, Circuits and Systems, 2006, pp. 506-509, doi: 10.1109/ICECS.2006.379836.
• Zlatanovici R., Kao S., and Nikolic B. 2009, “Energy–delay optimization of 64-bit carry-lookahead adders with a 240 ps 90 nm CMOS design example”, IEEE J. Solid-State Circuits, vol. 44, no. 2, 569–583.
• Govindaraj, V & Ramesh, J 2017, “An Improved Low Transition Test Pattern Generator for Low power Applications”, Design Automation for Embedded Systems, vol. 21, no. 3, December, 247-263.
• Govindaraj, V & Aruna Devi B, J 2021, “Machine learning based power estimation method for CMOS VLSI circuits” , Applied Artificial Intelligence, vol. 35, no. 13, October, 1043-1055.
• V. Govindaraj, K. Manoharan, K. L. Prabha, S. Dhanasekar and K. Sreekanth,2022 “Minimum Power Test Pattern Generator for Testing VLSI Circuits”, 6th International Conference on Devices, Circuits and Systems (ICDCS), 2022, pp. 27-31, doi: 10.1109/ICDCS54290.2022.9780773.
• S. Dubey and G. Verma 2020, “Analysis of Basic Adder with Parallel Prefix Adder”, First IEEE International Conference on Measurement, Instrumentation, Control and Automation (ICMICA), 2020, pp. 1-6, doi: 10.1109/ICMICA48462.2020.9242842.
• D. R. A, S. K. R, S. Deb, V. R. M, S. V and S. S, 2021 “Design and Analysis of High-Performance Carry Skip Adder using Various Full Adders”, Smart Technologies, Communication and Robotics (STCR), 2021, pp. 1-5, doi: 10.1109/STCR51658.2021.9588863.