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Year 2019, Volume: 19 Issue: 2, 158 - 165, 01.07.2019

Nuray Sağlam Fırat Kaçar

Abstract

References

  • 1. B. Mealy, F. Tappero, "Free Range VHDL", 2012. Available from: URL: http://www.gstitt.ece.ufl.edu/courses/eel4712/labs/free_range_vhdl.pdf.
  • 2. E. Sarıtaş, S. Karataş, "Her Yönüyle FPGA ve VHDL", Palme Yayıncılık, Ankara, Türkiye, 2015.
  • 3. R. Sahani, S. Gupta, N. Kishore, "FPGA In Embedded System And Its Application", IJIRT, vol. 1, no. 12, 2015.
  • 4. Module Design of Embedded Processors. Available from: URL: https://nptel.ac.in/courses/Webcourse-contents/IIT%20Kharagpur/Embedded%20systems/Pdf/Lesson-20.pdf. Dec, 2018.
  • 5. P. Vanjare, P. Pandey, February 2016, "Design and Implementation of 64-bit ALU using VHDL", International Journal of Engineering and Management Research, vol. 6, no. 1, pp. 500-502, 2016.
  • 6. R. M. Rewatkar, A. V. Khode, A. S. Kalinkar, P. S. Bangde, S. D. Potey, " Design and Simulation of High Speed, less area 64-Bit ALU using Efficient Technique", International Journal on Recent and Innovation Trends in Computing and Communication, vol. 4, no. 4, pp. 326-330, 2016.
  • 7. R. Chetia, K. C. D. Sarma, G. Baruah, "Behavioural Design and Synthesis of 64 BIT ALU using Xilinx ISE", IOSR-JECE, vol. 7, no. 4, pp. 37-41, Sept-Oct, 2013. https://doi.org/10.9790/2834-0743741
  • 8. P. Bhanusree, G. B. Sai, Y. A. Kumar, K. S. Kumar, "VHDL Implementation Of 64-bit ALU", IOSR-JECE, vol. 7, no. 4, pp. 14-17, Sept-Oct, 2013. https://doi.org/10.9790/2834-0741417
  • 9. M. P. Mahajan, P. G. Salunke, Y. M. Gaikwad, V. P. Jagtap, "Design and Simulation of 64 bit ALU", IJARECE, vol. 4, no. 4, pp. 1049-1051, Jan, 2015.
  • 10. R. Prabhakar, C. Rekha, "VLSI Design and Implementation of Arithmetic and Logic Unit Using VHDL", International Journal of Engineering and Science, vol. 3, no. 10, pp. 62-67, Oct, 2013.
  • 11. R. Uma, V. Vijayan, M. Mohanapriya, S. Paul, "Area, Delay and Power Comparison of Adder Topologies", International Journal of VLSI design & Communication Systems, vol. 3, no. 1, pp. 153-168, Febr, 2012. https://doi.org/10.5121/vlsic.2012.3113
  • 13. Hardware algorithms for arithmetic modules. Available from: URL: http://www.aoki.ecei.tohoku.ac.jp/arith/mg/algorithm.html#fsa_csa. Dec, 2018. 14. Altera® Corparation University Program, "DE2-70 Development and Education Board User Manual". Available from: URL: https://www.terasic.com.tw/attachment/archive/226/DE2_70_User_manual_v105.pdf.
  • 15. Altera® Corparation, "Introduction to the Quartus® II Software version 10.0", Available from: URL: https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/manual/intro_to_quartus2.pdf. 2012.

Design and Simulation of 64 Bit FPGA Based Arithmetic Logic Unit

Year 2019, Volume: 19 Issue: 2, 158 - 165, 01.07.2019

Nuray Sağlam Fırat Kaçar

Abstract

DOI: 10.26650/electrica.2019.18052


Arithmetic Logic Unit (ALU) is the essential part of the Central Processing Unit (CPU) core which performs arithmetical operations such as addition, subtraction, division, multiplication etc., logical operations such as and, or, xor etc. and shift-rotate operations. The CPU performance is directly related to the performance of ALU.
In this study, the 64-bit ALU has been designed by using the Very High Speed Integrated Circuits Hardware Description Language (VHDL) and Altera Field Programmable Gate Array (FPGA) families, synthesized and simulated with the help of Altera Quartus II (Intel, Santa Clara, CA, USA)  v13.0sp1 and Modelsim-Altera v10.1d (Intel, Santa Clara, CA, USA)  software. Many different studies are given about ALU Design and Implementation with the use of FPGA architecture and VHDL language. The difference of this study from recent studies is that the proposed design allows the processing of the signed numbers. Also, Conditional Sum Adder (COSA) is used in addition operation instead of Carry Ripple Adder (CRA) or Carry Look-ahead Adder (CLA) because of its benefit in fast addition and less propagation delay of Carry Chain.

Cite this article as:  Sağlam Bedir N, Kaçar F. Design and Simulation of 64 Bit FPGA Based Arithmetic Logic Unit. Electrica 2019; 10.26650/electrica.2019.18052.

Keywords

FPGA VHDL arithmetic logic unit design

References

  • 1. B. Mealy, F. Tappero, "Free Range VHDL", 2012. Available from: URL: http://www.gstitt.ece.ufl.edu/courses/eel4712/labs/free_range_vhdl.pdf.
  • 2. E. Sarıtaş, S. Karataş, "Her Yönüyle FPGA ve VHDL", Palme Yayıncılık, Ankara, Türkiye, 2015.
  • 3. R. Sahani, S. Gupta, N. Kishore, "FPGA In Embedded System And Its Application", IJIRT, vol. 1, no. 12, 2015.
  • 4. Module Design of Embedded Processors. Available from: URL: https://nptel.ac.in/courses/Webcourse-contents/IIT%20Kharagpur/Embedded%20systems/Pdf/Lesson-20.pdf. Dec, 2018.
  • 5. P. Vanjare, P. Pandey, February 2016, "Design and Implementation of 64-bit ALU using VHDL", International Journal of Engineering and Management Research, vol. 6, no. 1, pp. 500-502, 2016.
  • 6. R. M. Rewatkar, A. V. Khode, A. S. Kalinkar, P. S. Bangde, S. D. Potey, " Design and Simulation of High Speed, less area 64-Bit ALU using Efficient Technique", International Journal on Recent and Innovation Trends in Computing and Communication, vol. 4, no. 4, pp. 326-330, 2016.
  • 7. R. Chetia, K. C. D. Sarma, G. Baruah, "Behavioural Design and Synthesis of 64 BIT ALU using Xilinx ISE", IOSR-JECE, vol. 7, no. 4, pp. 37-41, Sept-Oct, 2013. https://doi.org/10.9790/2834-0743741
  • 8. P. Bhanusree, G. B. Sai, Y. A. Kumar, K. S. Kumar, "VHDL Implementation Of 64-bit ALU", IOSR-JECE, vol. 7, no. 4, pp. 14-17, Sept-Oct, 2013. https://doi.org/10.9790/2834-0741417
  • 9. M. P. Mahajan, P. G. Salunke, Y. M. Gaikwad, V. P. Jagtap, "Design and Simulation of 64 bit ALU", IJARECE, vol. 4, no. 4, pp. 1049-1051, Jan, 2015.
  • 10. R. Prabhakar, C. Rekha, "VLSI Design and Implementation of Arithmetic and Logic Unit Using VHDL", International Journal of Engineering and Science, vol. 3, no. 10, pp. 62-67, Oct, 2013.
  • 11. R. Uma, V. Vijayan, M. Mohanapriya, S. Paul, "Area, Delay and Power Comparison of Adder Topologies", International Journal of VLSI design & Communication Systems, vol. 3, no. 1, pp. 153-168, Febr, 2012. https://doi.org/10.5121/vlsic.2012.3113
  • 13. Hardware algorithms for arithmetic modules. Available from: URL: http://www.aoki.ecei.tohoku.ac.jp/arith/mg/algorithm.html#fsa_csa. Dec, 2018. 14. Altera® Corparation University Program, "DE2-70 Development and Education Board User Manual". Available from: URL: https://www.terasic.com.tw/attachment/archive/226/DE2_70_User_manual_v105.pdf.
  • 15. Altera® Corparation, "Introduction to the Quartus® II Software version 10.0", Available from: URL: https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/manual/intro_to_quartus2.pdf. 2012.
There are 13 citations in total.

Details

Primary Language English
Subjects Engineering
Journal Section Articles
Authors

Nuray Sağlam This is me

Fırat Kaçar

Publication Date July 1, 2019
Published in Issue Year 2019 Volume: 19 Issue: 2

Cite

APA Sağlam, N., & Kaçar, F. (2019). Design and Simulation of 64 Bit FPGA Based Arithmetic Logic Unit. Electrica, 19(2), 158-165.
AMA Sağlam N, Kaçar F. Design and Simulation of 64 Bit FPGA Based Arithmetic Logic Unit. Electrica. July 2019;19(2):158-165.
Chicago Sağlam, Nuray, and Fırat Kaçar. “Design and Simulation of 64 Bit FPGA Based Arithmetic Logic Unit”. Electrica 19, no. 2 (July 2019): 158-65.
EndNote Sağlam N, Kaçar F (July 1, 2019) Design and Simulation of 64 Bit FPGA Based Arithmetic Logic Unit. Electrica 19 2 158–165.
IEEE N. Sağlam and F. Kaçar, “Design and Simulation of 64 Bit FPGA Based Arithmetic Logic Unit”, Electrica, vol. 19, no. 2, pp. 158–165, 2019.
ISNAD Sağlam, Nuray - Kaçar, Fırat. “Design and Simulation of 64 Bit FPGA Based Arithmetic Logic Unit”. Electrica 19/2 (July 2019), 158-165.
JAMA Sağlam N, Kaçar F. Design and Simulation of 64 Bit FPGA Based Arithmetic Logic Unit. Electrica. 2019;19:158–165.
MLA Sağlam, Nuray and Fırat Kaçar. “Design and Simulation of 64 Bit FPGA Based Arithmetic Logic Unit”. Electrica, vol. 19, no. 2, 2019, pp. 158-65.
Vancouver Sağlam N, Kaçar F. Design and Simulation of 64 Bit FPGA Based Arithmetic Logic Unit. Electrica. 2019;19(2):158-65.
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