XOR VE FAZ/FREKANS DEDEKTÖR PLL İLE MASTER-SLAVE FAZ SENKRONİZASYON METODU

Year 2022, Volume: 21 Issue: 41, 80 - 94, 28.06.2022

Zeynep Kaplanoğlu Çantı , Serhan Yarkan

https://doi.org/10.55071/ticaretfbd.1008028

Abstract

Faz kilitli döngü (PLL), iletişimde teknolojinin ilerlemesine önemli ölçüde katkıda bulunan bir tekniktir. İlk uyumlu modülasyon sistemleri geliştirildiğinden beri elektronik mühendisliğinde faz ve frekans senkronizasyon sorunları mevcuttur. Bu makale, PLL'nin temel ayrıntılarını vermektedir. Kontrol sistemleri ve dijital iletişim için geçerli olan temel PLL ilkesinin kısa bir özetini sağlar. Ayrıca PLL bileşenlerini ve bunlar arasındaki karşılaştırmayı da bildirir. PLL'ler, doğru zaman esasını kurtarmaktan ve süreçleri senkronize etmekten sorumludur. Uygulama ihtiyaçlarına göre, master-slave en basit ve en çok kullanılan seçim olmak üzere farklı saat dağıtım stratejileri geliştirildi. Senkronizasyon için en aktif senkronizasyon tekniklerinden biri olduğu için PLL teknikleri seçilmiştir. Bu makale, MATLAB'ın Simulink'i, simulasyon yöntemi ve devre tasarımı ve PLL'yi senkronize etmek için matematiksel çözümler içermektedir.

Keywords

Faz kilitli döngü, voltaj kontrollü osilatör, XOR Faz dedektörü, faz/frekans dedektörü, şarj pompası faz kilitli döngü.

MASTER SLAVE PHASE SYNCHRONIZATION METHOD WITH XOR AND PHASE/FREQUENCY DETECTOR PLL

Abstract

Phase-locked loop (PLL) is a technique which has contributed significantly toward the technology advancement in communication. Phase and frequency synchronization problems have been present in electronic engineering since the first coherent modulation systems were developed. This paper gives basic details of PLL. It provides brief summary of the basic PLL principle applicable to control systems and digital communication. It also reports components of PLL and comparison among them. PLLs are responsible for recovering the correct time basis and synchronizing the processes. According to the application needs, different clock distribution strategies were developed, with the master-slave being the simplest and most used choice. PLL techniques is chosen for synchronization, since it is one of the most active synchronization techniques. This article contains Simulink of the MATLAB, simulation method and circuit design and mathematical solutions to synchronize PLL.

Keywords

Phase locked loop, voltage controlled oscillator, XOR Phase detector, phase/frequency detector, charge pump.

References

• Ayat, M., Babaei, B., Atani, R. E., Mirzakuchaki, S. & Zamanlooy, B. (2010, April, 11-14). Design of a 100MHz – 1.66GHz, 0.13µm CMOS phase locked loop. 2010 International Conference on Electronic Devices, Systems and Applications, Malaysia, 154-158. https://doi.org/10.1109/icedsa.2010.5503082.
• De Brabandere, K., Loix, T., Engelen, K., Bolsens, B., Van den Keybus, J., Driesen, J. & Belmans, R. (2006, November, 6-10). Design and operation of a phase-locked loop with Kalman estimator-based filter for single-phase applications. IECON 2006 - 32nd Annual Conference on IEEE Industrial Electronics, Paris, 525-530. https://doi.org/10.1109/iecon.2006.348099.
• Guan-Chyun, H. & Hung, J. (1996). Phase-locked loop techniques. A survey. IEEE Transactions on Industrial Electronics, 43(6), 609-615. https://doi.org/10.1109/41.544547.
• Kailuke, A. C., Agrawal, P. & Kshirsagar, R. (2014, January, 9-11). Design of phase frequency detector and charge pump for low voltage high frequency PLL. 2014 International Conference on Electronic Systems, Signal Processing and Computing Technologies, India, 74-78. https://doi.org/10.1109/icesc.2014.21.
• Karimi-Ghartemani, M., Ooi, B. & Bakhshai, A. (2011). Application of enhanced phase-locked loop system to the computation of Synchrophasors. IEEE Transactions on Power Delivery, 26(1), 22-32. https://doi.org/10.1109/tpwrd.2010.2064341.
• Lata, K., & Kumar, M. (2013). ALL digital phase-locked loop (ADPLL): A survey. International Journal of Future Computer and Communication, 1(10). 551-554. https://doi.org/10.7763/ijfcc.2013.v2.225.
• Leonov, G. A., Kuznetsov, N. V., Yuldashev, M. V. & Yuldashev, R. V. (2015). Hold-in, pull-in, and lock-in ranges of PLL circuits: Rigorous mathematical definitions and limitations of classical theory. IEEE Transactions on Circuits and Systems I: Regular Papers, 62(10), 2454-2464. https://doi.org/10.1109/tcsi.2015.2476295.
• Li, L., Wu, X. & Han, J. (2017). Design of 4GHz CMOS charge-pump phased-locked loop based on the Simulink behavioral simulation. Proceedings of the 2017 2nd International Conference on Automation, Mechanical and Electrical Engineering (AMEE 2017), 70-73. https://doi.org/10.2991/amee-17.2017.14.
• Majeed, K. A. & Kailath, B. J. (2013). A novel phase frequency detector for a high frequency PLL design. Procedia Engineering, 64, 377-384. https://doi.org/10.1016/j.proeng.2013.09.110.
• Monteiro, L., Dos Santos, R. & Piqueira, J. (2003). Estimating the critical number of slave nodes in a single-chain PLL network. IEEE Communications Letters, 7(9), 449-450. https://doi.org/10.1109/lcomm.2003.817322.
• Pawar, S.N., & Mane, P.B. (2017, December, 1-2). Wide band PLL frequency synthesizer: A survey. 2017 International Conference on Advances in Computing, Communication and Control (ICAC3), India, 1-6. https://doi.org/10.1109/icac3.2017.8318773.
• Piqueira, J.R. (2020). Master-slave Topologies with phase-locked loops. Wireless Communications and Mobile Computing, 2020, 1-12. https://doi.org/10.1155/2020/2727805.
• Piqueira, J.R., Caligares, A.Z. & Monteiro, L.H. (2007). Double-frequency jitter figures in master–slave PLL networks. AEU - International Journal of Electronics and Communications, 61(10), 678-683. https://doi.org/10.1016/j.aeue.2007.01.004.