Performance Evaluation of FPGA-Based Design of Modified Chua Oscillator

Year 2024, Volume: 6 Issue: 4, 249 - 256

Muhammed Furkan Taşdemir , Anna Litvinenko , İsmail Koyuncu , Filips Capligins

https://doi.org/10.51537/chaos.1466919

Abstract

The chaotic systems are one of the most important areas that increasing the popularity and are actively used in several fields. One of the most essential structures in chaotic systems is chaotic oscillator which generates chaotic signals. IQ-Math and floating point number systems are one of the preferred number standards. Presented in this study, the Modified Chua chaotic oscillator has been designed to work on FPGA chips using fixed point and floating point number systems. Euler numeric algorithm has been used for the design of the Modified Chua chaotic oscillator. The first section of the study, Modified Chua chaotic system based on fixed point has been composed the model in the Matlab Simulink and transformed to VHDL with the help of Matlab HDL Coder Toolbox. The second section of the study, Modified Chua chaotic oscillator has been designed with VHDL based on floating point. Modified Chua chaotic oscillators which are composed with two different number standards have been tested using Xilinx ISE Design Tools in VHDL. Modified Chua chaotic oscillators which have two different numbers standards and designed, are synthesized for Virtex-6 on ML605 FPGA development board with Xilinx ISE Design Tools 14.2 program. Values that are achieved from the process of synthesizing and maximum operating frequency have been presented. As a result, the study has obtained that fixed point number standard maximum operating frequency is 50.242 MHz and floating point number standard maximum operating frequency is 273.631 MHz.

Keywords

Chaotic oscillators, Euler Algorithm, FPGA chips, VHDL

Ethical Statement

The authors declare that they have no conflict of interest.

Supporting Institution

Riga Technical University

Thanks

Thank you to Riga Technical University for their support.

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